1. Field of the Invention
The present invention relates generally to an on-chip testing integrated circuit and a method for testing semiconductor memory or other integrated circuits in several multiple testing modes.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an outline of a configuration of a conventional semiconductor memory device capable of performing reading and writing data. Main components of this device and operation thereof are described in brief in the following.
In a standard reading/writing operation mode, an X address buffer 5 receives an X address signal applied to X address input terminals AX and applies it to an X decoder 2. A Y address buffer 6 receives a Y address signal applied to Y address input terminals AY and applies it to a Y decoder 3. In writing operation, input data applied to data input/output terminals DT is applied to a memory cell in a memory array 1 specified by the X decoder 2 and the Y decoder 3, through an input/output buffer 7 and a sense amplifier 4. On the other hand, in reading operation, data is read by the sense amplifier 4 from a memory cell in the memory array 1 specified by the X decoder 2 and the Y decoder 3 and is outputted from the data input/output terminals DT through the input/output buffer 7. A control circuit 8 receives a control signal applied from control signal input terminals CS through a control buffer 9 and applies the control signal to each component to perform the above described operation.
In addition to the above described standard operation mode, the semiconductor memory device is sometimes operated under certain special modes. The special modes are set, for example, in such cases as a reliability evaluation test at the time of shipment from a factory, a partial performance test of a circuit in a shortened operating time and a reading of chip identifying information.
For example, in a case of EEPROM (Electrically Erasable and Programmable Read only Memory), there are various special modes, as shown in a following Table 1. In the Table 1, approximate time required for executing an each special mode is described.
TABLE 1 ______________________________________ Special Mode (EEPROM) Required Time ______________________________________ 1. Evaluation test of the number of several hours times of rewriting (Automatic E/W) .about.dozens of days 2. Evaluation test of memory holding several hours (Automatic High Temperature Test) .about.dozens of days 3. Short test .about.1 .mu.sec Writing 4. Silicon signature .about.1 .mu.sec Reading Correction circuit cut 5. E.E.C. Syndrome external output .about.1 .mu.sec Parity bit external output 6. Check on an amount of shifts of a threshold voltage in a memory .about.1 .mu.sec cell transistor 7. Evaluation test of resistance several hours of a memory cell .about.several days 8. Simplified final test -- 9 Chip erase test -- ______________________________________
In the EEPROM, the evaluation test of the number of rewriting and the evaluation test of memory holding are especially important among the special modes shown in the Table 1, and thus it takes time to perform those tests.
In addition, in a paper published by H. McAdams, et al., and will be described later, examples of special modes with respect to dynamic RAM are seen, and which are shown in a following table 2.
TABLE 2 ______________________________________ Special modes (dynamic RAM) ______________________________________ 1. 8 BIT PARALLEL READ & WRITE 2. STATIC REFRESH DISTURB 3. FIELD LEAKAGE (STATIC) 4. FIELD LEAKAGE (DYNAMIC) 5. EXTERNAL SENSE AMP TIMING 6. REDUNDANCY ROLL CALL 7. SENSE AMP MARGIN 8. RESET TO MEMORY MODE 9. EXTERNAL OSC. TO VBB PUMP 10. OVERVOLTAGE DETECTOR TEST ______________________________________
As an further example of such special modes is described in a paper "A Sub 100 ns Static 64K CMOS EPROM With On-Chip Test Functions" presented by M.W. Kneeht et al., in ISSC (International Solid-State Circuits Conference) of IEEE held Feb. 23, 1983.
In order to designate such a special mode, conventionally, a method is employed, in which a plurality of optional external terminals including an address input terminal, a data input/output terminal, a control signal input terminal and the like are connected with a plurality of high voltage detection circuits and a high voltage is applied to any of the terminals to designate a special mode corresponding to the terminal concerned.
Referring to FIG. 1, four high voltage detection circuits 10 are connected to the X address input terminals AX, the data input/output terminals DT and the control signal input terminals CS and when any of the circuits detects a high voltage, a high voltage detection signal HV is applied to the control circuit 8. The control circuit 8 receives the high voltage detection signal HV and performs a control operation to carry out the corresponding special mode.
FIG. 2 is a schematic diagram showing one example of a conventional high voltage detection circuit. This high voltage detection circuit is shown as being connected to the control signal input terminal CS shown in FIG. 1 and it comprises a plurality of n channel MOS transistors Q1 to Q4 connected in series between one terminal 30 of the control signal input terminals CS and the ground GND, as well as an inverter 31. Only three transistors Q1 to Q3 are shown in the figure but, in effect, three or more transistors are connected. The transistors Q1 to Q3 have the gates connected to the respective drains, whereby diodes are formed. The transistor Q4 has its gate connected to the control circuit 8 and a reset signal is applied from the control circuit 8 at the time of resetting. The inverter 31 is connected to a connection point N1 between the transistors Q3 and Q4 and its output signal, that is, the high voltage detection signal HV is applied to the control circuit 8.
Now, operation of the high voltage detection circuit thus constructed is described.
When a high voltage is applied to the terminal 30 and a voltage of the connection point N1 exceeds a threshold of the inverter 31, the output signal, that is, the high voltage detection signal HV of the inverter 31 changes to a low level from a high level. When the supply voltage is DC 5V, the level of this high voltage is, for example, approximately 9V. The control circuit 8 receives the high voltage detection signal HV of the low level and recognizes that the special mode predetermined in correspondence with this terminal 30 is designated. Since it is necessary to continuously apply the high voltage detection signal HV to the control circuit 8 during operation of the special mode, it is necessary to continue to apply the high voltage to the terminal 30.
FIG. 3 is a block diagram for explaining a test function of a 1-M bit dynamic RAM described in a paper "A 1-M Bit CMOS Dynamic RAM With Design-For Test Functions" by H. McAdams et al., in IEEE Journal of Solid-State Circuits (Vol. Sc. 21), Oct., 1986.
Referring to FIG. 3, an RAS signal terminal RAS is connected to an input of a high voltage detection circuit 81 and a test control logic 82 is connected to an output of the high voltage detection circuit 81. Address input terminals A3 to A6 are connected to address buffers 84, respectively and the address buffers 84 are connected to test address latches 85, respectively. Test address latches 85 are connected to a test function decoder 83. The output of the high voltage detection circuit 81 is connected to each of control inputs of the address buffer 84 and the output of the test control logic 82 is connected to each of control inputs of the test address latches 85.
A main operation is now described. When a high voltage is detected by the high voltage detection circuit 81, a code for specifying a test function applied to the address input terminals A3 to A6 is latched by the test address latches 85. The test function decoder 83 specifies one test out of tests 1 to 9 by decoding the code latched by the test address latches 85.
In the case of specifying a special mode in the conventional semiconductor memory device shown in FIG. 1, the number of special modes, or the number of different kinds of special modes permitted to be specified is limited by the number of external input terminals. In addition, since it is necessary to continue to apply the high voltage to the external terminals, a special mode to be related with a terminal whose voltage has been at the high level and should be changed to a low level can not be set.
Furthermore, in the case of specifying a test mode in the dynamic RAM shown in FIG. 3, the test mode which is being executed can not be confirmed during the execution of the test mode because the address buffers 84 outputting a signal in only one direction are used. As for an EEPROM, for example, it sometimes takes time to perform a rewritable process count evaluation test or a high temperature acceleration test under self testing. On the occasion of such test, it sometimes happens that a long time will have passed without noticing an erroneously set mode because there is no confirming the special mode which is being carried out during the test. Even if the special mode is set correctly, the setting could be changed due to various causes (such as unstable supply voltage, a mistake by an operator and the like) during the execution of the special mode.